A system on a chip (SoC) is a circuit that integrates a plurality of components and/or electronic systems on a single substrate. SoCs comprise two main classes when it comes to designing of the SoCs—functionality, and timing; where functionality covers functions and verification of the SoC while timing covers the timing conditions necessary for proper operation of the SoCs.
With the advent of technology, SoC verification problems have largely been solved; however, the timing closure problems have remained the same. One reason is because the development of a timing specification (generally called timing constraints) is still a manual process which invariably results in incomplete or incorrect timing constraints. Also, with increased clocking complexity, shrinking geometries and multiple operational modes of the SoCs, the timing constraints development is tedious and error prone. Most of the SoC designs are delayed and/or failed due to timing constraints problems, yet there is no efficient automated timing constraints solution available in the market.
To solve the timing issues, design teams spend many tedious hours/months in managing the timing constraints (also called Synopsys Design Constraints, or SDC) for each hierarchical block, the full SoC, for each operational mode and finally for different phases of the design cycle. It is difficult to measure the exact amount of time that is spent on constraints development and subsequent refinement as the process is fragmented and depends on size and complexity of the design. Oftentimes, the timing constraints are developed bottom up starting with each block while a top level hardware description language is still being developed. Creating the top level timing constraints based on the lower level block's timing constraints is a manual process and very tedious and time consuming.
What is needed in the art is a method of timing constraints development which is not tedious, time consuming and error prone.